The present invention generally pertains to scrambling of binary data and is particularly directed to keystream generation utilizing one or more feedback shift register structures.
Binary data may be scrambled (encrypted) by processing the binary data with a keystream. Typically a binary data signal and the keystream are added modulo-2 on a bit-by-bit basis by an exclusive-OR (XOR) gate logic element to produce a scrambled binary data signal. The keystream generator typically produces a keystream by processing an initializing binary encryption key containing a plurality of key data bits. The scrambled binary data signal may be descrambled by adding modulo-2 to the scrambled signal an identical keystream, generated synchronously by an identical keystream generator that is initialized with the same binary encryption key.
A prior art keystream generator utilizing a feedback shift register structure, includes a feedback shift register, having input, intermediate and output stages through which data bits are shifted serially in response to a clock signal, a plurality of logic elements respectively located between predetermined pairs of register stages, means for feeding the data bit shifted from the output stage into the input stage and into predetermined ones of the logic elements in accordance with a polynomial code, wherein the logic elements process a data bit shifted from the preceding stage with the data bit fedback from the output stage in accordance with the polynomial code for input into the succeeding register stage; and means for processing the data bits shifted from a predetermined stage to provide a keystream. The key data bits of the encryption key are loaded in parallel into the shift register structure to initialize the operation of the keystream generator. The processing means include a memory, such as a read only memory (ROM) that provides individual keystream bits in accordance with a memory address made up of data bits shifted from a plurality of the stages of the shift register. In one such prior art keystream generator, data bits shifted from two separate feedback shift registers are combined to make up the memory address.